Master Physical Design Engineering Lead (up to $800k pkg)
Master Physical Design Engineering Lead (up to $800k pkg)
Hands-on semiconductor physical design leadership across ASIC programs, including physical design, STA, DFT, packaging, EDA flows, and validation. Requires multiple advanced-node tape outs, scripting, and U.S. work authorization without sponsorship.
Master Physical Design Engineering Lead (up to $800k package)
Total package up to $800k (Base + bonus + stock)
Locations: San Jose, CA, Irvine, CA or Fort Collins, CO
Introduction
Are you a seasoned Engineer who excels at guiding complex semiconductor programs across areas such as physical design, STA, DFT, and packaging and a passion for working on bleeding-edge AI and high-performance silicon? Have you delivered enough chips to recognize hidden issues in EDA reports before they impact schedules, and can you clearly explain both the technical root cause and the long term solution? Do you enjoy deep technical discussions with engineering teams while also providing clear, high level summaries to management?
If this sounds like you, and you want to work on advanced compute and infrastructure silicon, this role may be an excellent match.
Top Reasons to Work With Us
Support customers building cutting edge ASICs in AI, HPC, networking, and storage
Collaborate with highly experienced cross functional engineering and technology teams
Influence the development of next generation semiconductor technologies
Take ownership of customer success from initial engagement through production
Shape design methodologies, best practices, and implementation strategies
Be part of a supportive, collaborative environment that values technical leadership
The Role / Responsibilities
As a senior technical leader, (NOTE: prior leadership experience NOT required) you will guide customer ASIC programs and ensure successful delivery of highly complex designs. (Approximately 80% hands on, 20% technical leadership).
Your responsibilities will include:
Leading end to end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring up, and production
Advising customer teams on EDA best practices, design flows, and methodologies, including hosting Q&A sessions with technical experts
Identifying risks related to quality, schedule, or dependencies and coordinating mitigation plans with internal and external teams
Running physical design validation flows to ensure incoming customer netlists meet strict tape out quality requirements
Staying up to date on new technologies, IP developments, and application trends
Working closely with marketing, sales, legal, and compliance teams on program related discussions
Collaborating with and supporting other engineering teams as needed
Essential Skills
Multiple tape outs at advanced process nodes
Ability to analyze PPA tradeoffs across library components, architectures, and implementation strategies
Strong understanding of low power design techniques and power management
Hands on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packaging
Programming or scripting experience
Excellent communication skills
Bonus Points For
Exposure to SERDES communication protocols
Experience in logic design, chip architecture, microarchitecture, Verilog RTL development, front end verification, DRC, and logic synthesis
Knowledge of DFT methods including scan, memory BIST, and repair