Staff Physical Design Engineer (up to $400k pkg)
Staff Physical Design Engineer (up to $400k pkg)
Hands-on ASIC physical design or STA work supporting AI/ML and high-performance silicon programs, with tape-out validation, EDA flows, and cross-functional collaboration. Requires multiple ASIC tape-outs, scripting, and U.S. work authorization without sponsorship.
Staff ASIC Engineer (Physical Design OR STA)
Total package up to $400k (Base up to $200k + bonus + stock)
Total first year realistic income $350-400k.
Locations: San Jose, CA, Irvine, CA or Fort Collins, CO
Introduction
Are you an experienced ASIC engineer with strong expertise in physical design or STA, and a passion for working on bleeding-edge AI and high-performance silicon? Do you enjoy diving into complex EDA reports, identifying issues early, and collaborating with top-tier engineering teams to deliver next-generation chips?
If you're excited about contributing to advanced AI/ML accelerators and infrastructure silicon, this role offers the opportunity to work at the forefront of semiconductor innovation.
Top Reasons to Work With Us
- Support customers building next-generation AI/ML, HPC, and infrastructure ASICs
- Work on cutting-edge silicon for AI workloads, including large-scale compute and accelerator architectures
- Collaborate with highly experienced cross-functional engineering teams
- Gain exposure to advanced nodes, chiplet architectures, and high-performance design methodologies
- Contribute to customer program success from early engagement through production
- Be part of a collaborative, technically strong environment
The Role / Responsibilities
As a Staff ASIC Engineer, you will work closely with senior engineers and internal teams to support customer ASIC programs focused on advanced AI and compute silicon. This is a primarily hands-on role, with opportunities to grow into broader technical ownership over time.
Your responsibilities will include:
- Assisting in the execution of customer AI/ML ASIC programs across design, test, packaging, fabrication, bring-up, and production
- Supporting customer teams with EDA tools, design flows, and methodology best practices for high-performance silicon
- Helping identify risks in quality, schedule, or dependencies and contributing to mitigation efforts
- Running physical design or STA validation flows to ensure designs meet stringent tape-out standards for advanced nodes
- Collaborating with cross-functional teams to resolve complex implementation challenges in AI and compute architectures
- Staying current with emerging AI silicon trends, IP, and implementation methodologies
- Supporting program communication across engineering and internal partner teams
Essential Skills
- Experience with multiple ASIC tape-outs (advanced nodes preferred)
- Strong understanding of PPA tradeoffs, especially in high-performance designs
- Knowledge of low power design and power management in compute-intensive systems
- Hands-on experience in physical design or STA, including relevant EDA tools and flows
- Exposure to broader ASIC flows (logic simulation, test, packaging)
- Scripting experience (TCL, shell, or similar)
- Strong communication and collaboration skills
Bonus Points For
- Experience with AI/ML accelerators, HPC, or large-scale compute SoCs
- Exposure to SERDES or high-speed interfaces
- Experience in RTL design, microarchitecture, or front-end flows
- Knowledge of DFT (scan, MBIST, repair)