Senior Physical Design Engineering Lead
Summary
Lead customer ASIC programs with about 80% hands-on work and 20% technical leadership, including physical design validation, EDA best practices, and risk mitigation. Requires 10+ years, physical design or STA, multiple tape-outs, scripting, and U.S. work authorization.
Highlights
- Benefits
- Health, dental and vision insurance, life and disability insurance, FSA and HSA, 401(k) match, ESPP
- Experience
- 10+ years in physical design or STA, EDA tools and flows, multiple tape-outs, programming or scripting
- Number of Openings
- 2
Job description
Principal and Master Physical Design Engineering Leads (2 Openings)
Total packages: $500,000 to $800,000 (Base + Bonus + Stock)
Locations: Sillicon Valley, CA
The Role / Responsibilities
As a senior technical leader, (NOTE: prior leadership experience NOT required) you will guide customer ASIC programs and ensure successful delivery of highly complex designs. (Approximately 80% hands on, 20% technical leadership).
Top Reasons to Work With Us
Join the best and brightest in the field: lead complex customer engagements and influence next-generation chip development, tackling the industry's most challenging ASIC challenges and powering tomorrow's AI and high-performance computing systems.
Your responsibilities will include:
- Driving end-to-end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring-up, and production
- Managing physical design validation flows to ensure incoming customer netlists meet strict tape-out quality requirements
- Hosting informative sessions with technical experts and advising customer teams on EDA best practices, design flows, and methodologies
- Identifying risks related to quality, schedule, or dependencies and coordinating mitigation plans with internal and external teams
Essential Skills Over 10+ Years of Experience:
- Hands-on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packaging
- Multiple tape-outs at advanced process nodes
- Ability to analyze PPA tradeoffs across library components, architectures, and implementation strategies
- Thorough understanding of low power design techniques and power management
- Programming or scripting experience
- Excellent communication skills
A Plus if you Have:
- Exposure to SERDES communication protocols
- Experience in logic design, chip architecture, microarchitecture, Verilog RTL development, front-end verification, DRC, and logic synthesis
- Knowledge of DFT methods including scan, memory BIST, and repair